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datasheet most ? clock interface idt5v80001 idt? most ? clock interface 1 idt5v80001 rev s 083109 description the idt5v80001 is a high performance clock interface for use in most ? (media oriented systems transport) enabled systems. it can be used in two modes: generating a master clock for the ring, or performing clock/data recovery in a slave node. features ? packaged in 20-pin tssop ? -40 to +85c temperature range (industrial) ? compliant to aec q100 ? operating voltage of 3.3 v ? 5 volt tolerant input for fot ? low jitter generation ? power-down tri-state mode ? advanced, low-power cmos process block diagram crystal oscillator mclk x2 x1 master pll cdr pll input_copy s1 s0 bypass fot_in most_din fot_out 0 1 0 1 mux oem rclk retiming reset
idt5v80001 most ? clock interface synthesizers idt? most ? clock interface 2 idt5v80001 rev s 083109 pin assignment frequency selection tables * fot_in must be present in order to generate rclk and retimed (rclk) most_din. pin descriptions 13 4 12 5 11 8 rclk vdd 16 3 s1 1 x2 gnd input_copy nc 14 2 7 fot_out mclk 15 6 20-pin tssop x1 gnd oem most_din vdd 10 9 bypass lfr 17 18 19 20 fot_in s0 lf reset s1 s0 operating frequency (rclk) mode sampling frequency 0 0 45.1584 mhz most 25 44.1 khz 0 1 49.152 mhz most 25 48 khz 1 0 90.3168 mhz most 50 44.1 khz 1 1 98.304 mhz most 50 48 khz oem mclk output source for retiming block 0 low rclk (slave node) 1 running mclk (master node) oem node bypass fot_out 0 slave 0 retimed (rclk) most_din * 1fot_in 1 master 0 retimed (mclk) most_din 1fot_in pin name type pin description 1 x2 input connect to 21.504 mhz crystal. 2 x1 input connect to 21.504 mhz crystal. 3 reset input low to reset cdr pll. internal pull-up resistor. 4 vdd power connect to 3.3 v supply. 5 fot_out output output for fiber optic most transceiver. 3.3 v lvttl levels. 6 gnd power connect to ground. 7 s1 input frequency select input pin. see table above. no internal pull-up or pull-down resistor. 8 fot_in input input to device from fiber optic most transceiver. 3.3 v lvttl levels, 5 v tolerant. 9 s0 input frequency select input pin. see table above. no internal pull-up or pull-down resistor.
idt5v80001 most ? clock interface synthesizers idt? most ? clock interface 3 idt5v80001 rev s 083109 operation the idt5v80001 performs clock generation and recovery for either a master or slave node in a most ring. it provides a interface between a controller (typically implemented in an asic or fpga) and the fiber optic transceiver (fot). when used in a master node (oem = high), the master pll synthesizes a frequency of twice the most data rate as the mclk output, and also reclocks the data from the controller that is input on the fot_in pin to the input_copy output. the output data on fot_out is the most_din data retimed to mclk if bypass is driven low, or the fot_in data if bypass is driven high. simultaneously, the device recovers the clock from data on the fot_in pin and outputs a 2x clock on rclk. in a slave node, oem is set low and the mclk output is disabled. data from the controller (fot_in) is retimed using the recovered clock and output on the input_copy. if bypass is driven high, the contro ller data (fot_in) is also transmitted on the fot_out output but is not retimed to rclk. if bypass is driven low, the most_din data is retimed and transmitted on the fot_out output. to recover the clock from the data stream, the two plls work together. the lock sequence from power on is: 1 . crystal oscillator starts and stabilizes. 2 . master (frequency synthesis) pll starts and locks to the crystal. 3 . cdr pll starts and locks to the master pll to obtain a frequency operation point. 4 . activity is detected on fot_in. 5 . cdr pll phase-locks to incoming data. extreme conditions, such as electrical transients, phase steps or brief dropouts on the fot_in pin may cause the cdr pll to unlock. if this occurs and the controller begins to experience data erro rs, it should set reset low for at least 50 ns to restart the data lock sequence from step 3. 10 lf input loop filter connection for cdr pll. 11 lfr input loop filter return. connected to ground internally. 12 bypass input mux control to bypass cdr pll. active high. no internal pull-up or pull-down resistor. 13 oem input high to enable mclk. see table above. no internal pull-up or pull-down resistor. 14 mclk output master clock output. clean clock derived from crystal. see table above. weak pull-down when oem = 0. 15 gnd power connect to ground. 16 rclk output recovered clock out. see table above. 17 vdd power connect to 3.3 v supply. 18 input_copy output retimed copy of fot_in input. 19 most_din input most data input. 20 nc ? no connect. do not connect this pin to anything. pin name type pin description
idt5v80001 most ? clock interface synthesizers idt? most ? clock interface 4 idt5v80001 rev s 083109 external components the idt5v80001 requires a minimum number of external components for proper operation. decoupling capacitor a decoupling capacitor of 0.01f must be connected between each vdd pins and the ground plane, as close to these pins as possible. for optimum device performance, the decoupling capacitor should be mounted on the component side of the pcb. crystal the idt5v80001 requires a 21.504 mhz parallel resonant crystal. recommended devices are: crystal load capacitors the device crystal connections should include pads for capacitors from x1 to ground and from x2 to ground. these capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. the value (in pf) of these crystal caps should equal (c l -12 pf)*2. in this equation, c l = crystal load capacitance in pf. for the specified 16 pf load capacitance, each crystal capacitor would be 8 pf [(16-12) x 2 = 8]. external loop filter an external loop filter is required for operation of the cdr pll. recommended components are: r s = 1210 ? , 1% tolerance c s = 10 nf, use capacitor with a non-piezoelectric dielectric. recommended type is panasonic ech-u01103gx5 or equivalent. series termination resistor termination should be used on the fot_out, mclk, rclk, and input_copy output (pins 5, 14, 16, and 18 respectively). to series terminate a 50 ? trace (a commonly used trace impedance) place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) the 0.01f decoupling capacitors should be mounted on the component side of the board as close to the vdd pin as possible. no vias should be used between decoupling capacitor and vdd pin. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. 2) the external crystal should be mounted just next to the device with short traces. 3) the external loop filter components should be mounted close to the idt5v80001 and away from digital signals, switching power supply components, and other sources of noise. 4) to minimize emi, 33 ? series termination resistors should be placed close to the clock outputs. 5) an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. other signal traces should be routed away from the idt5v80001. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. external loop filter manufacturer package part # abracon 5x7 mm ceramic aah-363-21.504mhz ndk 3.2x5 mm ceramic exs00a-cg00294 9 10 11 12 r s c s lf lfr
idt5v80001 most ? clock interface synthesizers idt? most ? clock interface 5 idt5v80001 rev s 083109 absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the idt5v80001. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd 7 v inputs and outputs -0.5 v to vdd+0.5 v input (fot_in only) 7 v storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature -40 +85 c power supply voltage (measured with respect to gnd) +3.0 +3.3v +3.6 v power supply ramp time 4 ms
idt5v80001 most ? clock interface synthesizers idt? most ? clock interface 6 idt5v80001 rev s 083109 dc electrical characteristics unless stated otherwise, vdd = 3.3 v 10% , ambient temperature -40 to +85 c parameter symbol conditions min. typ. max. units operating supply current idd no load, f rclk = 49.152 mhz 35 ma high level input voltage v ih fot_in, most_din 2 5.5 v reset , bypass, oem, s0, s1 2.0 vdd+0.3 low level input voltage v il fot_in, most_din -0.3 0.8 v reset , bypass, oem, s0, s1 -0.3 0.8 high level output voltage v oh fot_out only, i oh = -2 ma 2.4 v mclk, rclk, input_copy i oh = -100 a vdd-0.2 low level output voltage v ol fot_out only, i oh = 2 ma 0.4 v mclk, rclk, input_copy i oh = 100 a 0.2 short circuit current i os fot_out 35 ma input capacitance c in fot_in, most_din, reset , bypass, oem, s0, s1 510pf nominal output impedance z out fot_out, mclk, rclk, input_copy 20 ? on-chip pull-up or pull-down resistor r p reset 500 k ?
idt5v80001 most ? clock interface synthesizers idt? most ? clock interface 7 idt5v80001 rev s 083109 timing requirements parameter symbol conditions min. typ. max. units crystal frequency f in 21.504 mhz input rise time t r s1=0, s0=0 (see fig. 1) 10.0 ns s1=0, s0=1 (see fig. 1) 9.2 s1=1, s0=0 (see fig. 1) 5.0 s1=1, s0=1 (see fig. 1) 4.6 input fall time t f s1=0, s0=0 (see fig. 1) 10.0 ns s1=0, s0=1 (see fig. 1) 9.2 s1=1, s0=0 (see fig. 1) 5.0 s1=1, s0=1 (see fig. 1) 4.6 input pulse width variation (fot_in and most_din) t pwv s1=0, s0=0 (see fig. 2) 16.4 31.1 ns s1=0, s0=1 (see fig. 2) 15.1 28.5 s1=1, s0=0 (see fig. 2) 8.2 15.6 s1=1, s0=1 (see fig. 2) 7.5 14.3 average input pulse width distortion (fot_in and most_din) t apwd s1=0, s0=0 (see fig. 2) -3.4 +7.0 ns s1=0, s0=1 (see fig. 2) -3.1 +6.5 s1=1, s0=0 (see fig. 2) -1.7 +3.5 s1=1, s0=1 (see fig. 2) -1.6 +3.3 one-sigma data dependent jitter (fot_in) t ddj s1=0, s0=0 (see fig. 3) 0 3.4 ns s1=0, s0=1 (see fig. 3) 0 3.1 s1=1, s0=0 (see fig. 3) 0 1.7 s1=1, s0=1 (see fig. 3) 0 1.6 one-sigma uncorrelated jitter t uj s1=0, s0=0 (see fig. 4) 0 1000 ps s1=0, s0=1 (see fig. 4) 0 920 s1=1, s0=0 (see fig. 4) 0 500 s1=1, s0=1 (see fig. 4) 0 460 cdr reset time t reset (see fig. 5) 50 ns
idt5v80001 most ? clock interface synthesizers idt? most ? clock interface 8 idt5v80001 rev s 083109 timing diagrams figure 1: rise and fall time definitions figure 3: data dependent jitter figure 5: reset timing definition figure 2: pulse width variation and average pulse width distortion figure 4: uncorrelated jitter figure 6: test and measurement setup vdd t r signal t f 0v 90% of vdd 10% of vdd trigger tx (node n-1) node n t ddj t reset 1.5 v 1.5 v vdd 0v reset rclk locked to most data rclk locked to mclk rclk 2ui + t pwv(max) 2ui + t pwv(min) 1ui + t pwv(max) 1ui + t pwv(min) 1ui 2ui (bit period) 3ui (occurs at preambles) t pwv(max) t pwv(min) t apwd t apwd t apwd v oh v ol 1.5 v trigger tx (node n-1) node n t uj dut 0.1f c load vdds gnd r load 2 kohm 10pf output
idt5v80001 most ? clock interface synthesizers idt? most ? clock interface 9 idt5v80001 rev s 083109 figure 7: duty cycle definitions figure 9: propagation delay figure 11: bypass timing definition figure 8: power up and pll lock timing figure 10: clock timing figure 12: most data?clock example vdd t 2 clock output t 1 0v 1.5 v duty cycle, d= t 2 t 1 t pd fot_in 1.5 v 1.5 v fot_out note: reset = h, bypass = h, oem = l or h t blh 1.5 v 1.5 v vdd 0v fot_out t bhl most_din data fot_in data fot_in data bypass most_din fot_in oem most_din data fot_in data reset vdd 0v vdd 0v 0 ms power up time vco ramp time pll locked t clock t dlock note: fot_in must be running and stable during vco ramp time. rclk t cdr t sk t jit fot_in rclk input_copy 0011 coding violation 01 most input (retimed) recovered clock
idt5v80001 most ? clock interface synthesizers idt? most ? clock interface 10 idt5v80001 rev s 083109 ac electrical characteristics unless stated otherwise, vdd = 3.3 v 10% , ambient temperature -40 to +85 c parameter symbol conditions min. typ. max. units crystal frequency f in 21.504 mhz output frequency error due to frequency synthesis 0 ppm output clock duty cycle d figures 6 and 7 45 50 55 % output rise time t r s1=0, s0=0 (see fig. 1) 5.0 ns s1=0, s0=1 (see fig. 1) 4.6 s1=1, s0=0 (see fig. 1) 2.5 s1=1, s0=1 (see fig. 1) 2.3 output fall time t f s1=0, s0=0 (see fig. 1) 5.0 ns s1=0, s0=1 (see fig. 1) 4.6 s1=1, s0=0 (see fig. 1) 2.5 s1=1, s0=1 (see fig. 1) 2.3 output pulse width variation (fot_out) t pwv s1=0, s0=0 (see fig. 2) 21.2 23.1 ns s1=0, s0=1 (see fig. 2) 19.5 21.2 s1=1, s0=0 (see fig. 2) 10.6 11.5 s1=1, s0=1 (see fig. 2) 9.8 10.6 average output pulse width distortion (fot_out) t apwd s1=0, s0=0 (see fig. 2) -500 +500 ps s1=0, s0=1 (see fig. 2) -460 +460 s1=1, s0=0 (see fig. 2) -250 +250 s1=1, s0=1 (see fig. 2) -230 +230 one-sigma data dependent jitter (rclk) t ddj s1=0, s0=0 (see fig. 3) 0 220 ps s1=0, s0=1 (see fig. 3) 0 200 s1=1, s0=0 (see fig. 3) 0 110 s1=1, s0=1 (see fig. 3) 0 100 one-sigma uncorrelated jitter (rclk) t uj s1=0, s0=0 (see fig. 4) 0 95 ps s1=0, s0=1 (see fig. 4) 0 90 s1=1, s0=0 (see fig. 4) 0 45 s1=1, s0=1 (see fig. 4) 0 45 power-up time t clock pll lock-time from 90% vdd to rclk = mclk, (see fig. 8) 200 s t dlock pll lock-time from beginning of fot_in input to stable rclk output, (see fig. 8) 400 s propagation delay (fot_in to fot_out) t pd (see fig. 9) 3 4 5 ns propagation delay (fot_in to rclk) t cdr (see fig. 10) tbd tbd tbd ns skew, recovered clock to retimed input t sk (see fig. 10) -250 0 +250 ps one-sigma clock period jitter mclk 0 50 ps
idt5v80001 most ? clock interface synthesizers idt? most ? clock interface 11 idt5v80001 rev s 083109 thermal characteristics rclk peak-to-peak jitter with respect to fot_in t jit -500 0 +500 ps bypass high-to-low to fot_out t bhl (see fig. 11) tbd tbd ns bypass low-to-high to fot_out t blh (see fig. 11) tbd tbd ns parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 93 c/w ja 1 m/s air flow 78 c/w ja 3 m/s air flow 65 c/w thermal resistance junction to case jc 20 c/w parameter symbol conditions min. typ. max. units
idt5v80001 most ? clock interface synthesizers idt? most ? clock interface 12 idt5v80001 rev s 083109 marking diagrams notes: 1. ?z? is the device step (1 to 2 characters). 2. yyww is the last two digits of the year and week that the part was assembled. 3. ?$? is the assembly mark code. 4. ?g? after the two-letter package code designates rohs compliant package. 5. ?i? at the end of part number indicates industrial temperature range. 6. ?w3? denotes automotive grade. 7. bottom marking: country of origin if not usa. 1 10 11 20 idt5v800 01pggi zyyww$ 1 10 11 20 idt5v800 01pggi zyyww$ w3
idt5v80001 most ? clock interface synthesizers idt? most ? clock interface 13 idt5v80001 rev s 083109 package outline and package dimensions (20-pin tssop, 4.4mm narrow body) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with a ?g? after the two-letter package code are the pb-free configuration and are rohs compliant. ?w3? denotes automotive grade. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 5v80001pggi see page 8 tubes 20-pin tssop -40 to +85 c 5V80001PGGI8 tape and reel 20-pin tssop -40 to +85 c 5v80001pggw3 see page 8 tubes 20-pin tssop -40 to +85 c 5v80001pggw38 tape and reel 20-pin tssop -40 to +85 c index area 1 2 20 d e1 e seating plane a1 a a2 e - c - b aaa c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a--1.20--0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 6.40 6.60 0.252 0.260 e 6.40 basic 0.252 basic e1 4.30 4.50 0.169 0.177 e 0.65 basic 0.0256 basic l 0.45 0.75 0.018 0.030 0 8 0 8 aaa -- 0.10 -- 0.004
idt5v80001 most ? clock interface synthesizers idt? most ? clock interface 14 idt5v80001 rev s 083109 revision history rev. originator date description of change a j. gazda 08/29/06 preliminary datasheet. b j. gazda 09/19/06 changed block diagram and pinout; c j. gazda 09/25/06 changed from 16-pin tssop to 20- pin tssop; added timing diagrams; changed pinout and block diagrams. d j. gazda 09/27/06 new block diagram; changed pinout; added propagation delay, skew, and clock jitter specs; changed high/low in put/output level specs. e j. gazda 11/02/06 changed temperature rating from -4 0/+85 to -40/+105 c; added ?mode? and ?sampling frequency? to frequency selection table. f j. gazda 12/14/06 added ?operation? section; added ?external loop filter? diagram; added reset# pin; various modifications to ?external components? text. g j. gazda 02/15/07 added feature bullet of ?5 v tolerant input for fot?; add crystal caps and ground to block diagram; added ?weak pull-down when oem=0? statement to mclk pin description. h j. gazda 03/22/07 added ndk crystal part number; changed ?mclk? to ?rclk? in the conditions for ?data to clock jitter? spec. j j. gazda 05/31/07 removed c p reference on external loop filter descriptions; removed one capacitor from ?cdr pll? in block diagram. k j. gazda 06/22/07 reversed ?1? and ?0? on the mux in the block di agram; removed the bar from ?bypass?; added the text ?no pull-up? to pin descriptions 7, 9, 12, and 13; removed ?data to clock jitter? spec from ac char table. l j. gazda 10/09/07 removed ?lock? pin. m t. nana 12/17/07 updates to timing diagrams; adde d ?timing requiremnets? table; updates to pin descriptions; multiple updates to ac/dc char tables; added figure 7. n t. nana 12/26/07 updates to block diagram and timing diagrams; added new ?operation? information; added another oem table for bypass and fot_out; updates to ac/dc char tables and ?timing requirementts? table; added ?reset timing defi nition? (fig. 8) and ?bypass timing definition? (fig. 9) diagrams. p t. nana 01/08/08 updates to dc electrical char ta ble; one-sigma jitter specs added to ?timing requirements? table; updates to timing diagrams; added jitter and propagation delay timing diagrams; added one-sigma jitter specs to ac electrical char table; q t. nana 02/06/08 removed oem and mux from block diagram; updates to "operation" text; updated "propagation delay" diagram; added additional ?propagation delay? spec to ac char table. r 11/14/08 moved from preliminary to released. s d.l. 08/31/09 added automotive grade ordering info and marking diagram
? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp innovate with idt and accelerate your future netw orks. contact: www.idt.com idt5v80001 most ? clock interface synthesizers

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